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Verilog_HDL_Synthesis_A_Practical_Primer
- verilog综合经典教程,verilog标准制定人写的书,推荐-verilog synthesis classic tutorials, verilog standard-setting people write books, recommended
pic
- 上传的是一个PIC代码,其包含PIC完整子模块,可以进行综合,对学习PIC很有帮助-Upload a PIC code, which contains a complete sub-PIC module can be integrated, very helpful for learning PIC
keyscan_test
- 针对机械式按键存在的抖动问题,用verilog HDL编写了一个采用防抖方案并对按键次数计数的模块,已经在ISE综合通过!-Keys exist for mechanical jitter, with verilog HDL prepared a program with anti-shake button and count the number of modules have been integrated by ISE!
VerilogHDL
- Verilog HDL设计要点在前面学习的基上, 通过本章十个阶段的练习,能逐步掌握Verilog HDL 设计的要点。可以先理解样板模块中每一条语句的作用,然后对样板模块进行综合前和综合后仿真,再独立完成每一阶段规定的练习。-Verilog HDL design points in the previous study based on ten stages of practice by this chapter, can gradually grasp the main points of
top1
- verilog可综合的图像旋转模块和testbench-verilog synthesizable testbench modules and image rotation
mips
- MIPs CPU,VERILOG代码,经过QUARTUS综合,时序分析,验证无误。-MIPS CPU
DDFS_verilog
- 直接数字频率综合器,采用ROM压缩法,经过FPGA验证和AISC实现-Direct digital frequency synthesizer, using ROM compression method, validation and AISC through FPGA Implementation
VerilogHDLxiayuwen
- Verilog HDL数字设计与综合 夏宇闻译(第二版)-Digital design and synthesis of Verilog HDL translation of Xia Yu Wen (Second Edition)
SRAM
- 语言:VHDL 功能:利用VHDL编程,实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的,如果不是此型号的SRAM需要对程序进行时序修改。 仿真工具:modelsim 综合工具:quartus -Language: VHDL function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it
I2C
- 语言:verilog 功能:用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路:一条串行数据线 SDA, 一条串行时钟线 SCL;串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s,快速模式下可达 400kbit/s ,高速模式下可达 3.4Mbit/s;在数据传输过程中,当时钟线为高电平时,数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化,会被认为是控制信号。 仿真工具:modelsim 综合工具:quartus -Language:
61EDA_C1910
- ARM9架构简单CORE实现,可以综合,有实现步骤和说明,Verilog代码编写-ARM9 CORE achieve simple structure, can be integrated, with implementation steps and instructions, Verilog coding
Synthesizable-Verilog-syntax
- 可综合的Verilog语法(剑桥大学,影印).-Synthesizable Verilog syntax (Cambridge, photocopying).
Verilog-HDL-Synthesis
- 学习如何使用Verilog HDL综合,进行时序分析-Verilog HDL Synthesis A Practical Primer
AsynFIFO
- Verilog 代码 异步FIFO,可综合,综合效率高,cumming的经典方法。-Verilog code for asynchronous FIFO, Cumming s the classic method.
Verilog-Digital-System-Design
- Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book
Verilog-HDL-synthesis
- Verilog HDL数字设计与综合 。详细介绍了Verilog设计数字系统-Digital Design and Verilog HDL synthesis. Details Verilog digital system design
verilog-RTLevel-Synthesis
- 本章详细的分析了寄存器传输级综合,ieee最新标准-IEEE Standard for Verilog® Register Transfer Level Synthesis
fenpinqi
- 200分频的verilog综合仿真源程序,以及仿真波形-200divition-200 points frequency integrated simulation verilog source code, and the simulation waveform-200divition
Verilog-FIFO
- 可综合的Verilog FIFO存储器,可以实现先如先出的设计-Synthesizable Verilog FIFO memory can be as-first-out design
Verilog_integer_reg
- 深入探讨verilog中integer与reg两者的区别,从综合与实现的角度介绍-Depth in the integer and reg verilog difference between the two, from the point of introduction and implementation of comprehensive